Name
Abstract | ||
|---|---|---|
In this paper, we propose an FPGA memory hierarchy based on the OpenCL memory model. The memory hierarchy allows application-specific memory optimizations during design compilation using information provided in OpenCL kernels. With the proposed memory hierarchy, FPGA application developers can focus on their designs in OpenCL kernel codes, and their designs can be synthesized into FPGA hardware via high-level synthesis. In the FPGA hardware, our proposed memory hierarchy handles memory management efficiently regardless of application types, and consequently, developers are free from designing application-specific memory hierarchies. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/HPCC-CSS-ICESS.2015.210 | 2015 IEEE 17TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS, 2015 IEEE 7TH INTERNATIONAL SYMPOSIUM ON CYBERSPACE SAFETY AND SECURITY, AND 2015 IEEE 12TH INTERNATIONAL CONFERENCE ON EMBEDDED SOFTWARE AND SYSTEMS (ICESS) |
Keywords | Field | DocType |
FPGA, Memory Hierarchy, OpenCL, High-level Synthesis, Data Reuse | Registered memory,Interleaved memory,Computer architecture,Memory hierarchy,Extended memory,Shared memory,Computer science,Parallel computing,Memory management,Memory map,Flat memory model | Conference |
ISSN | Citations | PageRank |
2576-3504 | 0 | 0.34 |
References | Authors | |
9 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsiang-Yu Tseng | 1 | 0 | 0.34 |
| Ssu-Ting Liu | 2 | 0 | 0.68 |
| Sheng-De Wang | 3 | 720 | 68.13 |