Name
Abstract | ||
|---|---|---|
Multiple errors are an increasing concern for designers. Multiple errors in the configuration memory have to be taken into account when a circuit is implemented on a SRAM-based FPGA. This paper reports on the impact of realistic multiple-bit errors in the configuration, with respect to the robustness of a processor with error detection mechanisms. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/LATW.2012.6261263 | LATW |
Field | DocType | Citations |
Dependability,Computer science,Field-programmable gate array,Static random-access memory,Electronic engineering,Error detection and correction,Robustness (computer science),Embedded system | Conference | 0 |
PageRank | References | Authors |
0.34 | 9 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohamed Ben Jrad | 1 | 6 | 1.93 |
| Régis Leveugle | 2 | 354 | 44.83 |