Name
Title | ||
|---|---|---|
A cross-layer design exploration of charge-recycled power-delivery in many-layer 3d-IC |
Abstract | ||
|---|---|---|
3D-IC technology brings both the opportunities to continue the historical trend of integration-level scaling and the challenges to deliver power reliably and efficiently. Voltage-stacking (V-S), a charge-recycled power delivery scheme that connects the different layers' supply/ground nets into a series stack, provides a scalable solution to the 3D-IC power delivery wall. While prior work has extensively discussed the implementations of V-S at circuit-level, a cross-layer study that examines its system-level implications is missing. In this paper, we start with a circuit implementation of a charge-recycled voltage regulator and build an architecture-level model to study the costs and benefits of utilizing V-S in 3D-IC. Our study shows that by significantly improving the EM-lifetime of C4 and TSV array (e.g., up to 5x) while only marginally increasing the average-case voltage noise (e.g., 0.75% Vdd IR drop), V-S provides a scalable solution for many-layer 3D-IC's power delivery challenge. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2744769.2744774 | DAC |
Keywords | Field | DocType |
3D stacking, Power distribution network, Voltage noise | Power network design,Computer science,Voltage optimisation,Electronic engineering,Voltage regulation,Three-dimensional integrated circuit,Electrical engineering,Low-dropout regulator,Constant power circuit,Voltage regulator,Switched-mode power supply | Conference |
ISSN | Citations | PageRank |
0738-100X | 2 | 0.39 |
References | Authors | |
8 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Runjie Zhang | 1 | 45 | 5.01 |
| Kaushik Mazumdar | 2 | 37 | 4.34 |
| Brett H. Meyer | 3 | 10 | 3.11 |
| Ke Wang | 4 | 160 | 10.89 |
| Kevin Skadron | 5 | 6188 | 384.18 |
| Mircea R. Stan | 6 | 3103 | 277.34 |