Name
Abstract | ||
|---|---|---|
In a network-on-chip (NoC) based manycore architecture, an off-chip data access (main memory access) needs to travel through the on-chip network, spending considerable amount of time within the chip (in addition to the memory access latency). In addition, it contends with on-chip (cache) accesses as both use the same NoC resources. In this paper, focusing on data-parallel, multithreaded applications, we propose a compiler-based off-chip data access localization strategy, which places data elements in the memory space such that an off-chip access traverses a minimum number of links (hops) to reach the memory controller that handles this access. This brings three main benefits. First, the network latency of off-chip accesses gets reduced; second, the network latency of on-chip accesses gets reduced; and finally, the memory latency of off-chip accesses improves, due to reduced queue latencies. We present an experimental evaluation of our optimization strategy using a set of 13 multithreaded application programs under both private and shared last-level caches. The results collected emphasize the importance of optimizing the off-chip data accesses. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2737924.2737989 | PLDI |
Keywords | Field | DocType |
Manycores,memory controller,off-chip accesses localization | Uniform memory access,Latency (engineering),Computer science,Cache,Queue,Chip,Real-time computing,Data access,Memory controller,CAS latency | Conference |
Volume | Issue | ISSN |
50 | 6 | 0362-1340 |
Citations | PageRank | References |
8 | 0.50 | 22 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Ding | 1 | 130 | 11.67 |
| Xulong Tang | 2 | 128 | 7.49 |
| Mahmut T. Kandemir | 3 | 7371 | 568.54 |
| Yuanrui Zhang | 4 | 180 | 15.48 |
| Emre Kultursay | 5 | 265 | 11.46 |