Name
Abstract | ||
|---|---|---|
This paper proposes a fast reconfiguration algorithm for the two-dimensional degradable mesh-connected processor arrays. The proposed algorithm simplifies a dynamic programming approach to construct logical columns. For each processing element lying in the logical columns, the calculation is reduced from five operations (one assignment, two additions and two comparisons) that are taken in the state-of-the-art to single assignment operation in most cases, or three operations (one assignment, one comparison and one addition) in worst case. Simulation results based on same benchmarks utilized in the state-of-the-art show that, the simplified algorithm runs faster by 28%, without loss of harvest. Moreover, the increase of the total interconnection length of the target array is acceptable. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/PAAP.2010.59 | PAAP |
Field | DocType | Volume |
Dynamic programming,Single assignment,Computer science,Parallel computing,Fault tolerance,Processing element,Interconnection,Very-large-scale integration,Control reconfiguration,Reconfiguration algorithm | Conference | null |
Issue | Citations | PageRank |
null | 1 | 0.36 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jing Wang | 1 | 410 | 41.91 |
| Wu Jigang | 2 | 764 | 86.18 |
| Yuanrui Zhang | 3 | 180 | 15.48 |
| Dakun Zhang | 4 | 41 | 9.22 |