Name
Abstract | ||
|---|---|---|
In this work, a compact model based on an analytical closed form solution of the 1D Poisson's equation for a double-gate Tunnel FET is derived. Furthermore, the current levels are estimated by implementing an algorithm based on the Kane's band-to-band tunneling model. A good agreement with numerical simulations for varying device parameters is demonstrated and the advantages and limitations of the modeling approach are investigated and discussed. The model is implemented in a Verilog-A based circuit simulator and basic circuit blocks like an inverter, a 2-bit half adder and a 15 stage ring oscillator are simulated to demonstrate the capabilities of the model. The switching energy of a Tunnel FET based circuit block is studied with Vdd scaling revealing interesting aspects of Tunnel FET circuit behavior. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ESSDERC.2015.7324708 | 2015 45th European Solid State Device Research Conference (ESSDERC) |
Keywords | Field | DocType |
compact modeling,DG-tunnel FET,Verilog-A,analytical closed form solution,1D Poisson equation,double-gate tunnel field effect transistor,Kane band-to-band tunneling model,circuit block,inverter,adder,ring oscillator,word length 2 bit | Inverter,Ring oscillator,Logic gate,Adder,Closed-form expression,Electronic engineering,Electronic circuit simulation,Scaling,Verilog-A,Materials science | Conference |
ISSN | ISBN | Citations |
1930-8876 | 978-1-4673-7133-9 | 0 |
PageRank | References | Authors |
0.34 | 2 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Arnab Biswas | 1 | 21 | 1.35 |
| Luca De Michielis | 2 | 0 | 0.34 |
| Antonios Bazigos | 3 | 6 | 3.44 |
| Adrian Mihai Ionescu | 4 | 4 | 3.30 |