Name
Abstract | ||
|---|---|---|
CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V nMOSFETs on Si with threshold voltage tunability. We also demonstrate planar-type Ge/strained SOI and InGaAs TFETs. The defect-less p(+)/n source junction formation with steep impurity profiles is a key for high performance TFET operation. |
Year | Venue | Keywords |
|---|---|---|
2015 | Proceedings of the European Solid-State Device Research Conference | MOSFET,Tunneling FET,Germanium,III-V semiconductors,Metal-Oxide-Semiconductor,Mobility,Interface states |
Field | DocType | ISSN |
Silicon on insulator,Logic gate,Wafer bonding,Electronic engineering,CMOS,MOSFET,Materials science,Quantum well,Threshold voltage,AND gate | Conference | 1930-8876 |
Citations | PageRank | References |
1 | 0.41 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shinichi Takagi | 1 | 3 | 9.69 |
| Mitsuru Takenaka | 2 | 4 | 6.86 |