Name
Abstract | ||
|---|---|---|
In this paper we propose the first practical fault attack on the time redundancy countermeasure for AES using a biased fault model. We develop a scheme to show the effectiveness of a biased fault model in the analysis of the time redundancy countermeasure. Our attack requires only faulty ciphertexts and does not assume strong adversarial powers. We successfully demonstrate our attack on simulated data and 128-bit time redundant AES implemented on Xilinx Spartan-3A FPGA. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1007/978-3-319-21476-4_13 | CONSTRUCTIVE SIDE-CHANNEL ANALYSIS AND SECURE DESIGN, COSADE 2015 |
Keywords | Field | DocType |
Cryptanalysis, Time redundancy, Biased faults, AES | Countermeasure,Computer science,Field-programmable gate array,Cryptanalysis,Redundancy (engineering),Fault attack,Fault model,Embedded system | Conference |
Volume | ISSN | Citations |
9064 | 0302-9743 | 15 |
PageRank | References | Authors |
0.61 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sikhar Patranabis | 1 | 71 | 16.67 |
| Abhishek Chakraborty | 2 | 48 | 7.18 |
| Phuong Ha Nguyen | 3 | 84 | 12.41 |
| Debdeep Mukhopadhyay | 4 | 28 | 2.02 |