Paper Info
Title
Multi-product floorplan and uncore design framework for chip multiprocessors
Abstract
Chip multiprocessors (CMPs) for server and high-performance computing markets are offered in multiple classes to satisfy various power, performance and cost requirements. As the number of processor cores on a single die grows, resources outside the “core”, such as the distributed last-level cache, on-chip memory controllers and network-on-chip (NoC) interconnecting these resources, which constitute the “uncore”, play an increasingly important role. While it is crucial to optimize the floorplan and uncore of each product class to achieve the best power-performance tradeoff, independent optimization may greatly increase the design effort, and undermine the savings ultimately achieved with a given total amount of optimization effort. This paper presents a novel multi-product optimization framework for next generation CMPs. Unlike traditional chip optimization techniques, we optimize the floorplan of multiple product classes at once, and ensure that the smaller floorplans can be obtained from larger ones by optimally removing, i.e., chopping, the unused parts.
Year
DOI
Venue
2015
10.1109/SLIP.2015.7171713
2015 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)
Keywords
Field
DocType
multiproduct floorplan,uncore design framework,chip multiprocessors,high-performance computing markets,distributed last-level cache,on-chip memory controllers,network-on-chip,NoC,power-performance tradeoff,multiproduct optimization framework,next generation CMP,chip optimization techniques
System on a chip,Cache,Computer science,Server,Uncore,Real-time computing,Chip,Bandwidth (signal processing),Multi-core processor,Floorplan,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
8
Authors
5
Name
Order
Citations
PageRank
Marco Escalante100.34
Andrew B. Kahng27582859.06
Michael Kishinevsky381467.81
Ümit Y. Ogras420315.03
Kambiz Samadi581743.11