Name
Title | ||
|---|---|---|
Efficient FPGA Implementation of Equalizer for Finite Interval Constant Modulus Algorithm |
Abstract | ||
|---|---|---|
This paper deals with the optimization of iterative algo- rithms with matrix operations or nested loops for hard- ware implementation in Field Programmable Gate Arrays (FPGA), using Integer Linear Programming (ILP). The method is demonstrated on an implementation of the Fi- nite Interval Constant Modulus Algorithm, proposed for 4G communication systems. We used two pipelined arith- metic libraries based on the logarithmic number system or the floating-point number system, using the widely known IEEE format for the floating-point calculations re- quired in the algorithm. Traditional approaches to the scheduling of nested loops lead to a relatively large code, which is unsuitable for FPGA implementation. This paper presents a new high-level synthesis methodology, which models both, iterative loops and imperfectly nested loops, by means of the system of linear inequalities. Moreover, memory access is considered as an additional resource constraint. Since the solutions of ILP formulated prob- lems are known to be computationally intensive, impor- tant part of the article is devoted to the reduction of the problem size. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/IES.2006.357480 | IES |
Field | DocType | Citations |
Computer science,Iterative method,Floating point,Parallel computing,High-level synthesis,Algorithm,Real-time computing,Integer programming,Linear programming,Logarithmic number system,Matrix multiplication,Nested loop join | Conference | 2 |
PageRank | References | Authors |
0.40 | 11 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| sůcha přemysl | 1 | 74 | 13.96 |
| hanzalek zdeněk | 2 | 101 | 22.42 |
| Antonin Hermanek | 3 | 24 | 4.13 |
| Jan Schier | 4 | 2 | 0.40 |