Name
Abstract | ||
|---|---|---|
Recently, single-ISA heterogemeous multi-core processors (SI-HMP) draw attention, pursuing optimal power-performance scaling. Leveraging differently optimized heterogeneous cores, SI-HMP can dynamically tune performance with minimal additional power consumption, or it can find maximum performance core combination with respect to a given power budget. However, the little-to-big, or big-to-little core switching has hidden costs. To properly scale up/down the power-performance, we should carefully analyze the actual performance gain, considering the multi-core processing model and inter-cluster communication. This paper reveals that there are some good and bad cases for core switching, and presents a possible way to achieve good power-performance scaling through big-little switching. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1145/2818613.2818745 | HotPower@SOSP |
Field | DocType | Citations |
Power budget,Simulation,Engineering,Power performance,Scaling,Reliability engineering,Power consumption | Conference | 4 |
PageRank | References | Authors |
0.47 | 7 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| See-hwan Yoo | 1 | 86 | 10.96 |
| YoonSeok Shim | 2 | 4 | 0.47 |
| Seunghac Lee | 3 | 4 | 0.47 |
| Sang-Ah Lee | 4 | 4 | 0.47 |
| Joongheon Kim | 5 | 611 | 81.49 |