Name
Abstract | ||
|---|---|---|
This paper proposes a new method to optimize a BCH error correction decoder in multi-channel configurations. We break the BCH decoding process into its three basic blocks: syndrome calculation, the error locator polynomial generation, and the roots of the error locator polynomial computation. While an existing multi-channel BCH decoder consists of several single-channel BCH decoders operating in parallel, this paper utilizes a pooled group of shared decoding blocks. By considering the frequency of errors, the proposed pooled group approach requires fewer hardware blocks than in a traditional multi-channel configuration with a negligible impact on performance. Combined with a specialized root finding unit for blocks with only 1 error, our scheme reduces hardware area by 47%--71% and dynamic power by 44%--59% with 2% performance degradation in typical NAND flash systems. With a constant hardware area, the proposed scheme can improve throughput by 3x--5x or NAND flash lifetime by 1.4x--4.5x.
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Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/CASES.2015.7324546 | International Conference on Compilers, Architectures, and Synthesis for Embedded Systems |
Keywords | Field | DocType |
multichannel BCH error decoding,BCH error correction decoder,multichannel configuration,error locator polynomial generation,specialized root finding unit,NAND flash systems | System on a chip,Polynomial,Computer science,Parallel computing,Field-programmable gate array,NAND gate,BCH code,Error detection and correction,Dynamic demand,Decoding methods | Conference |
ISSN | ISBN | Citations |
2381-1560 | 978-1-4673-8320-2 | 1 |
PageRank | References | Authors |
0.42 | 7 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Russ Dill | 1 | 1 | 0.42 |
| Aviral Shrivastava | 2 | 812 | 68.67 |
| Hyunok Oh | 3 | 457 | 40.49 |