Paper Info
Title
A sparse VLIW instruction encoding scheme compatible with generic binaries
Abstract
Very Long Instruction Word (VLIW) processors are commonplace in embedded systems due to their inherent lowpower consumption as the instruction scheduling is performed by the compiler instead by sophisticated and power-hungry hardware instruction schedulers used in their RISC counterparts. This is achieved by maximizing resource utilization by only targeting a certain application domain. However, when the inherent application ILP (instruction-level parallelism) is low, resources are under-utilized/wasted and the encoding of NOPs results in large code sizes and consequently additional pressure on the memory subsystem to store these NOPs. To address the resource-utilization issue, we proposed a dynamic VLIW processor design that can merge unused resources to form additional cores to execute more threads. Therefore, the formation of cores can result in issue widths of 2, 4, and 8. Without sacrificing the possibility of code interruptability and resumption, we proposed a generic binary scheme that allows a single binary to be executed on these different issue-width cores. However, the code size issue remains as the generic binary scheme even slightly further increases the number NOPS. Therefore, in this paper, we propose to apply a well-known stop-bit code compression technique to the generic binaries that, most importantly, maintains its code compatibility characteristic allowing it to be executed on different cores. In addition, we present the hardware designs to support this technique in our dynamic core. For prototyping purposes, we implemented our design on a Xilinx Virtex-6 FPGA device and executed 14 embedded benchmarks. For comparison, we selected a nondynamic/ static VLIW core that incorporates a similar stop-bit technique for its code compression. We demonstrate, while maintaining code compatibility on top of a flexible dynamic VLIW processor, that the code size can be significantly reduced (up to 80%) resulting in energy savings, and that the performance can be increased (up to a factor of three). Finally, our experimental results show that we can use smaller caches (2 to 4 times as small), which will further help in decreasing energy consumption.
Year
DOI
Venue
2015
10.1109/ReConFig.2015.7393361
2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)
Keywords
Field
DocType
static VLIW core,Xilinx Virtex-6 FPGA device,stop-bit code compression technique,dynamic VLIW processor design,resource-utilization issue,NOP encoding,instruction-level parallelism,RISC,instruction scheduling,low-power consumption,embedded systems,very long instruction word processors,generic binaries,sparse VLIW instruction encoding scheme
Instruction scheduling,Computer science,Very long instruction word,Parallel computing,Field-programmable gate array,Thread (computing),Real-time computing,Compiler,Processor design,Application domain,Encoding (memory),Embedded system
Conference
ISSN
Citations 
PageRank 
2325-6532
2
0.38
References 
Authors
12
7
Name
Order
Citations
PageRank
Anthony Brandon1274.10
Joost Hoozemans2193.77
Jeroen van Straten3103.07
Arthur Francisco Lorenzon4469.07
Anderson Luiz Sartor5317.67
Antonio Carlos Schneider Beck6273.42
Stephan Wong711912.80