Title
FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures.
Abstract
In theory, tools like VTR---a retargetable toolchain mapping circuits onto easily-described hypothetical FPGA architectures---could play a key role in the development of wildly innovative FPGA architectures. In practice, however, the experiments that one can conduct with these tools are severely limited by the ability of FPGA architects to produce reliable delay and area models---these depend on transistor-level design techniques which require a different set of skills. In this paper, we introduce a novel approach, which we call Fpresso, to model the delay and area of a wide range of largely different FPGA architectures quickly and with reasonable accuracy. We take inspiration from the way a standard-cell flow performs large scale transistor-size optimization and apply the same concepts to FPGAs, only at a coarser granularity. Skilled users prepare for \\fpresso locally optimized libraries of basic components with a variety of driving strengths. Then, ordinary users specify arbitrary FPGA architectures as interconnects of basic components. This is globally optimized within minutes through an ordinary logic synthesis tool which chooses the most fitting version of each cell and adds buffers wherever appropriate. The resulting delay and area characteristics can be automatically used for VTR. Our results show that \\fpresso provides models that are on average within some 10-20\\% of those by a state-of-the-art FPGA optimization tool and is orders of magnitude faster. Although the modelling error may appear relatively high,we show that it seldom results in misranking a set of architectures, thus indicating a reasonable modeling faithfulness.
Year
DOI
Venue
2016
10.1145/2847263.2847280
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Field
DocType
Citations 
Logic synthesis,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Fpga architecture,Granularity,Transistor,Electronic circuit,Transistor design,Toolchain
Conference
3
PageRank 
References 
Authors
0.41
13
5
Name
Order
Citations
PageRank
Grace Zgheib1216.40
Manana Lortkipanidze230.41
Muhsen Owaida3869.65
David Novo411012.88
Paolo Ienne52246199.26