Paper Info
Title
A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems.
Abstract
The advent of FPGA acceleration platforms with direct coherent access to processor memory creates an opportunity for accelerating applications with irregular parallelism governed by large in-memory pointer-based data structures. This paper uses the simple reference behavior of a linked-list traversal as a proxy to study the performance potentials of accelerating these applications on shared-memory processor-FPGA systems. The linked-list traversal is parameterized by node layout in memory, per-node data payload size, payload dependence, and traversal concurrency to capture the main performance effects of different pointer-based data structures and algorithms. The paper explores the trade-offs over a wide range of implementation options available on shared-memory processor-FPGA architectures, including using tightly-coupled processor assistance. We make observations of the key effects on currently available systems including the Xilinx Zynq, the Intel QuickAssist QPI FPGA Platform, and the Convey HC-2. The key results show: (1) the FPGA fabric is least efficient when traversing a single list with non-sequential node layout and a small payload size; (2) processor assistance can help alleviate this shortcoming; and (3) when appropriate, a fabric only approach that interleaves multiple linked list traversals is an effective way to maximize traversal performance.
Year
DOI
Venue
2016
10.1145/2847263.2847269
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Field
DocType
Citations 
Pointer (computer programming),Data structure,Tree traversal,Linked list,Shared memory,Computer science,Parallel computing,Real-time computing,Payload (computing),Embedded system,Payload,Cache coherence
Conference
12
PageRank 
References 
Authors
0.60
9
6
Name
Order
Citations
PageRank
Gabriel Weisz11448.30
Joseph Melber2120.60
Yu Wang3572.44
Kermin E. Fleming419015.12
Eriko Nurvitadhi539933.08
James C. Hoe62048141.34