Paper Info
Title
Just In Time Assembly of Accelerators.
Abstract
Despite the significant advancements that have been made in High Level Synthesis, the reconfigurable computing community has failed at getting programmers to use Field Programmable Gate Arrays (FPGAs). Existing barriers that prevent programmers from using FPGAs include the need to work within vendor specific CAD tools, knowledge of hardware programming models, and the requirement to pass each design through synthesis, place and route. In this paper we present a new approach that takes these barriers out of the design flows for programmers. Synthesis is eliminated from the application programmers path by becoming part of the initial coding process when creating the programming patterns that define a Domain Specific Language. Programmers see no difference between creating software or hardware functionality when using the DSL. A run time interpreter is introduced that assembles hardware accelerators within a configurable tile array of partially reconfigurable slots at run time. Initial results show the approach allows hardware accelerators to be compiled 100x faster compared to the time required to synthesize the same functionality. Initial performance results further show a compilation/interpretation approach can achieve approximately equivalent performance for matrix operations and filtering compared to synthesizing a custom accelerator.
Year
DOI
Venue
2016
10.1145/2847263.2847341
ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Keywords
Field
DocType
FPGA, Overlay, Just-In-Time Hardware Compilation
Computer science,Real-time computing,Design flow,Software,Domain-specific language,Computer architecture,Programming paradigm,High-level synthesis,Parallel computing,Field-programmable gate array,Place and route,Reconfigurable computing,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
9
Authors
3
Name
Order
Citations
PageRank
Sen Ma1235.31
Zeyad Aklah2202.59
David Andrews3216.90