Name
Title | ||
|---|---|---|
Exploiting parallelism of imperfect nested loops with sibling inner loops on coarse-grained reconfigurable architectures. |
Abstract | ||
|---|---|---|
Coarse-grained reconfigurable architecture (CGRA) is a promising platform for loop acceleration, but existing software pipelining methods cannot achieve satisfactory performance on a fair number of imperfect nested loops, especially those with sibling inner loops. To tackle this problem, this paper makes 2 contributions: 1) a 2-level pipelining method with an effective II optimization strategy for the imperfect loops with sibling inner loops; 2) a novel kernel compression method to reduce oversize kernel. Experiment results show that our approach can achieve much higher performance than the state-of-the-art approaches at acceptable costs. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ASPDAC.2016.7428054 | ASP-DAC |
Keywords | Field | DocType |
data compression,optimisation,parallel architectures,reconfigurable architectures,CGRA,II optimization strategy,coarse-grained reconfigurable architecture,kernel compression method,loop acceleration,loop parallelism | Kernel (linear algebra),Pipeline (computing),Imperfect,Software pipelining,Computer science,Parallel computing,Real-time computing,Acceleration,Nested loop join,For loop | Conference |
ISSN | Citations | PageRank |
2153-6961 | 0 | 0.34 |
References | Authors | |
12 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xinhan Lin | 1 | 11 | 2.62 |
| shouyi yin | 2 | 579 | 99.95 |
| leibo liu | 3 | 816 | 116.95 |
| Shaojun Wei | 4 | 555 | 102.32 |