Name
Abstract | ||
|---|---|---|
Polar codes are capacity-achieving error-correcting codes with an explicit construction that can be decoded with low-complexity algorithms. In this work, we show how the state-of-the-art low-complexity decoding algorithm can be improved to better accommodate low-rate codes. Dedicated hardware is added to efficiently decode new constituent codes. Also, we use polar code construction alteration to further improve the latency and throughput. A polar decoder for a (1024, 512) code is implemented on two different FPGAs. It has 25% lower latency over the previous work and a coded throughput of 436 Mbps and 638 Mbps on the Xilinx Virtex 6 and Altera Stratix IV FPGAs, respectively. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/SiPS.2015.7345007 | 2015 IEEE Workshop on Signal Processing Systems (SiPS) |
Keywords | Field | DocType |
polar decoder,capacity-achieving error-correcting codes,low-complexity decoding algorithm,polar code construction alteration,Altera Stratix IV FPGA,Xilinx Virtex 6 | Stratix,Concatenated error correction code,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Virtex,Polar code,Soft-decision decoder,Decoding methods,Throughput | Conference |
Citations | PageRank | References |
3 | 0.39 | 11 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pascal Giard | 1 | 244 | 17.57 |
| Gabi Sarkis | 2 | 253 | 17.23 |
| Claude Thibeault | 3 | 107 | 14.35 |
| Warren J. Gross | 4 | 1106 | 113.38 |