Title
Automatic design of domain-specific instructions for low-power processors
Abstract
This paper explores hardware specialization of low-power processors to improve performance and energy efficiency. Our main contribution is an automated framework that analyzes instruction sequences of applications within a domain at the loop body level and identifies exactly and partially-matching sequences across applications that can become custom instructions. Our framework transforms sequences to a new code abstraction, a Merging Diagram, that improves similarity identification, clusters alike groups of potential custom instructions to effectively reduce the search space, and selects merged custom instructions to efficiently exploit the available customizable area. For a set of 11 media applications, our fast framework generates instructions that significantly improve the energy-delay product and speed-up, achieving more than double the savings as compared to a technique analyzing sequences within basic blocks. This paper shows that partially-matched custom instructions, which do not significantly increase design time, are crucial to achieving higher energy efficiency at limited hardware areas.
Year
DOI
Venue
2015
10.1109/ASAP.2015.7245697
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Keywords
Field
DocType
automatic design,domain-specific instruction,low-power processor,hardware specialization,performance efficiency,energy efficiency,instruction sequence,loop body level,partially-matching sequence,code abstraction,merging diagram,similarity identification,potential custom instruction,search space,energy-delay product,partially-matched custom instruction
Computer architecture,Energy conservation,Abstraction,Performance efficiency,Computer science,Efficient energy use,Parallel computing,Exploit,Real-time computing,Custom instruction,Merge (version control),Low-power electronics
Conference
ISSN
Citations 
PageRank 
1063-6862
2
0.36
References 
Authors
22
5