Paper Info
Title
Mixed-signal implementation of differential decoding using binary message passing algorithms
Abstract
This paper presents the mixed-signal circuit implementation of reduced complexity algorithms for decoding low-density parity check (LDPC) codes. Based on modified differential decoding using binary message passing (MDD-BMP), binary addition using discrete-time digital circuits is replaced by continuous-time analog-current summation. Potential degradation due to the mismatch between current sources, P/N strength mismatch and inverter-threshold mismatch is considered in behavioural simulation and shown to be tolerable. Area estimates suggest a reduction from 0.27 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> to 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for the FG(273, 191) code. Finally, transistor level simulation of the FG(273, 191) code using TSMC 65 nm technology shows an efficiency of 0.56 pJ/bit.
Year
DOI
Venue
2015
10.1109/ASAP.2015.7245718
2015 IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Keywords
Field
DocType
analog circuits,binary messages,energy efficient,iterative decoding,LDPC,VLSI
Parity bit,Digital electronics,Analogue electronics,Low-density parity-check code,Computer science,Algorithm,Real-time computing,Mixed-signal integrated circuit,Decoding methods,Message passing,Binary number
Conference
ISSN
Citations 
PageRank 
1063-6862
0
0.34
References 
Authors
8
3
Name
Order
Citations
PageRank
Glenn Cowan196.71
Kevin Cushon200.68
Warren J. Gross31106113.38