Name
Abstract | ||
|---|---|---|
High cost of qualifying library standard cells on silicon wafer limits the number of test circuits on the test chip. This paper proposes a technique to share common load circuits among test circuits to reduce the silicon area. By enabling the load sharing, number of transistors for the common load can be reduced significantly. Results show up to 80% reduction in silicon area due to load area reduction. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ICEAC.2015.7352210 | 5th International Conference on Energy Aware Computing Systems & Applications |
Keywords | Field | DocType |
Standard cell qualification,library validation,delay chain,TEG circuit,on-silicon measurement | Circuit extraction,Circuit design,Electronic engineering,Application-specific integrated circuit,Standard cell,Mixed-signal integrated circuit,Engineering,Physical design,Electronic circuit,Integrated circuit | Conference |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaafar K. Al-Frajat | 1 | 0 | 0.34 |
| Wameedh Nazar Flayyih | 2 | 3 | 1.74 |
| Roslina Sidek | 3 | 12 | 2.24 |
| Khairulmizam Samsudin | 4 | 92 | 13.43 |
| Fakhrul Z. Rokhani | 5 | 35 | 9.25 |