Name
Title | ||
|---|---|---|
Design of high-performance, power-efficient optical NoCs using Silica-embedded silicon nanophotonics |
Abstract | ||
|---|---|---|
With on-chip electrical interconnects being marred by high energy-to-bandwidth costs, threatening multicore scalability, on-chip nanophotonics, which offer high throughput, yet energy-efficient communication, form an alternative attractive counterpart. In this paper we consider silicon nanophotonic components that are embedded completely within the silica (SiO2) substrate as opposed to prior-art that utilizes die on-surface silicon nanophotonics. As nanophotonic components now reside in the silica substrate's subsurface non-obstructive interconnect geometries offering higher network throughput can be implemented. First, we show using detailed simulations based on commercial optical tools that such Silicon-In-Silica (SiS) structures are feasible, derive their geometry characteristics and design parameters, and then demonstrate our proof of concept by utilizing a hybrid SiS-based photonic mesh-diagonal links network-on-chip topology. In pushing the performance envelope even more, we next develop (1) an associated contention-aware photonic adaptive routing function, and (2) a parallelized photonic channel allocation scheme, that in tandem further reduce message delivery latency. An extensive experimental evaluation, including utilizing traffic benchmarks gathered from full-system chip multiprocessor simulations, shows that our methodology boosts network throughput by up to 30.8%, reduces communication latency by up to 22.5%, and improves the throughput-to-power ratio by up to 23.7% when compared to prior-art. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ICCD.2015.7357077 | International Conference on Computer Design |
Keywords | Field | DocType |
full-system chip multiprocessor simulations,message delivery latency reduction,parallelized photonic channel allocation scheme,contention-aware photonic adaptive routing function,hybrid SiS-based photonic mesh-diagonal link network-on-chip topology,network throughput,silica substrate subsurface nonobstructive interconnect geometry,die on-surface silicon nanophotonics,energy-efficient communication,multicore scalability,energy-to-bandwidth costs,on-chip electrical interconnects,silica-embedded silicon nanophotonic component,high-performance power-efficient optical NoCs design,SiO2,Si | Computer science,Nanophotonics,Electronic engineering,Real-time computing,Chip,Proof of concept,Throughput,Interconnection,Multi-core processor,Photonics,Scalability | Conference |
Citations | PageRank | References |
1 | 0.35 | 16 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| elena kakoulli | 1 | 36 | 5.37 |
| Vassos Soteriou | 2 | 421 | 27.62 |
| Charalambos Koutsides | 3 | 2 | 1.38 |
| Kyriacos Kalli | 4 | 4 | 2.87 |