Paper Info
Title
A new encoding mechanism for low power inter-chip serial communication in asynchronous circuits
Abstract
Since asynchronous circuits consume power only when activities actually happen, the conventional serial communication scheme where the embedded clock is always transmitted and the clock and data recovery (CDR) circuit is continuously working is very wasteful for connecting asynchronous circuit cores. This paper proposes a new serial communication scheme for asynchronous circuits where the power consumption of the line drivers in the transmitter and the deserializer in the receiver are reduced to almost 0 for the period when no data is transmitted. The proposed scheme is based on a new encoding mechanism where four voltage levels are used in order to embed a clock signal explicitly and a new sampler that extracts the clock and data without using PLL/DLL based circuits. This paper shows overall ideas of the proposed scheme and some initial HSPICE simulation results using 28nm and 130nm device technologies.
Year
DOI
Venue
2015
10.1109/ICCD.2015.7357132
International Conference on Computer Design
Keywords
Field
DocType
Serial communication scheme for asynchronous circuits, Four voltage levels, Fine grain power control
Clock signal,Serial communication,Clock gating,Asynchronous communication,Asynchronous system,Computer science,Clock domain crossing,Electronic engineering,Real-time computing,Synchronous circuit,Asynchronous circuit
Conference
Citations 
PageRank 
References 
0
0.34
13
Authors
2
Name
Order
Citations
PageRank
Tomohiro Yoneda135341.62
Masashi Imai2367.63