Name
Abstract | ||
|---|---|---|
Modern communication systems are characterized by intensive computation signal processing algorithms. System-on-Chip implementations of these systems are generally based on Networks-on-Chip (NoC). The router and Network Interface (NI) are the main elements of the NoC, but the router is the architecture most discussed in the literature. Here, a NI + router microarchitecture is presented. Our router implementation outperforms the previous work in operational frequency by a 20%. The NI usually is assumed as a simple wrapper, although results in this work show that the NI can consume almost twice resources than the router. This indicates that further discussions must be carried out for the design of NoC-based communication systems.
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Year | DOI | Venue |
|---|---|---|
2016 | 10.1145/2881025.2889484 | ANCS |
Keywords | Field | DocType |
network interface,networks-on-chip,system-on-chip implementation,signal processing algorithm,NoC-based communication system,NI+router microarchitecture | Computer architecture,Computer science,Field-programmable gate array,Communications system,Computer network,Core router,Router,One-armed router,Computation,Embedded system,Network interface,Microarchitecture | Conference |
ISBN | Citations | PageRank |
978-1-4503-4183-7 | 0 | 0.34 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Remberto Sandoval-Arechiga | 1 | 6 | 2.23 |
| Ramon Parra-Michel | 2 | 84 | 12.86 |
| J. L. Vázquez-Avila | 3 | 6 | 1.89 |
| B. I. Gea-Garcia | 4 | 2 | 1.11 |