Name
Abstract | ||
|---|---|---|
The design limitations of a DLL-based fractional-N frequency synthesis are reviewed in this paper. A novel dual-loop delay-locked loop (DLL) fractional-N frequency synthesizer is presented. The proposed DLL architecture overcomes the integer-N limitation of the conventional DLL-based frequency multiplier, and achieves small frequency spacing while maintaining low jitter accumulation. A DLL-based digital-to-phase converter with a phase interpolator is employed as the first loop to provide modulated fractional reference clock and precise lower frequency injection signal. The fine phase/frequency spacing is achieved by applying delta-sigma modulation at the DLL digital-to-phase converter. Another MDLL is used as the second loop to suppress spurs in the modulated fractional reference signal and achieving high frequency output. To verify the proposed architecture, a system-level DLL model is built and simulate. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/CCECE.2015.7129170 | 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE) |
Keywords | Field | DocType |
DLL fractional-N frequency synthesizer,DLL fractional-M frequency synthesizer,delay-locked loop,integer-N limitation,DLL-based frequency multiplier,small frequency spacing,low jitter accumulation,digital-to-phase converter,phase interpolator,fractional reference clock,lower frequency injection signal,phase spacing,delta-sigma modulation,modulated fractional reference signal | Frequency synthesis,Control theory,Computer science,Frequency synthesizer,Modulation,Automatic frequency control,Frequency multiplier,Control engineering,Electronic engineering,Frequency modulation,Low jitter,Direct digital synthesizer | Conference |
ISSN | ISBN | Citations |
0840-7789 | 978-1-4799-5827-6 | 0 |
PageRank | References | Authors |
0.34 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haizheng Guo | 1 | 3 | 2.65 |
| Tadeusz Kwasniewski | 2 | 3 | 2.19 |