Name
Abstract | ||
|---|---|---|
A delay-locked loop (DLL) based period synthesis is described. The proposed synthesizer architecture uses a single-loop DLL with phase interpolators to generate wide range of output frequencies. For the first time, the proposed period synthesis does overcome the integer-N limitation of the conventional DLL-based frequency multiplier, and achieve a small phase/frequency step. The delta-sigma modulation technique is applied at the phase selection stage to achieve a fine phase resolution. The spur performance in the frequency domain is also analyzed based on CMOS implementation. A system-level period synthesizer is built to verify the proposed architecture. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/CCECE.2015.7129168 | Canadian Conference on Electrical and Computer Engineering |
Field | DocType | ISSN |
Frequency domain,Phase modulation,Computer science,Electronic engineering,Frequency synthesizer,Control engineering,Modulation,Frequency multiplier,CMOS,Frequency modulation,Direct digital synthesizer | Conference | 0840-7789 |
ISBN | Citations | PageRank |
978-1-4799-5827-6 | 0 | 0.34 |
References | Authors | |
4 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haizheng Guo | 1 | 3 | 2.65 |
| Tadeusz Kwasniewski | 2 | 3 | 2.19 |