Name
Title | ||
|---|---|---|
OPTIMAL ZERO-FORCING TRANSCEIVER DESIGN FOR MAXIMIZING BIT RATE SUBJECT TO A TOTAL TRANSMIT POWER CONSTRAINT |
Abstract | ||
|---|---|---|
In this paper, we design the optimal zero-forcingtransceiver that maximizes the transmission bit rate for multiple-input multiple-output (MIMO) channels. The transmission bit rate is maximized subject to a total power constraint for a given error rate. Instead of using the same input constella- tion size for all subchannels as in earlier designs, the bit al- location is also taken into consideration. The bit allocation and the zero-forcing transceiver are jointly designed for bit rate maximization. The optimal transceiver is obtained in a closed form. The bits are allocated according to the sub- channel signal to noise ratios. The larger the signal to noise ratio is, the more the number of bits are allocated. In the simulation, we have demonstrated that a higher bit rate can be achieved compared to previously reported methods. |
Year | Venue | Field |
|---|---|---|
2008 | European Signal Processing Conference | Transceiver,Audio bit depth,Control theory,Computer science,Signal-to-noise ratio,Communication channel,Real-time computing,Eb/N0,Transmission time,Harmonic Vector Excitation Coding,Bit error rate |
DocType | ISSN | Citations |
Conference | 2219-5491 | 1 |
PageRank | References | Authors |
0.37 | 8 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chien-Chang Li | 1 | 41 | 5.66 |
| Yuan-pei Lin | 2 | 760 | 74.13 |
| Shang-ho Tsai | 3 | 188 | 24.44 |
| P. P. Vaidyanathan | 4 | 4 | 1.06 |