Title
FPGA implementation of a MIMO DFE IN 40 GB/S DQPSK optical links
Abstract
In this paper, an FPGA implementation of a Multi Input Multi Output (MIMO) Decision Feedback equalizer (DFE) is proposed, for the electronic compensation of the impairments in 40Gb/s Intensity Modulated Direct Detection (IM/DD) optical communication links employing NRZ DQPSK signaling. The proposed equalizer is used for the electronic compensation the residual Chromatic Dispersion (CD) along the installed optically compensated optical paths. The required processing rate is achieved by applying intensive pipelining and parallelism in the original architecture of the equalizer. At the given processing rate, a 8-input 2-output DFE involving three taps feedforward filtering and two taps backward filtering is implemented on a single, cutting edge technology, Xilinx FPGA device,
Year
Venue
Keywords
2015
European Signal Processing Conference
DQPSK Optical Transmission,DFE equalization,FPGA implementation
Field
DocType
ISSN
Pipeline (computing),Computer science,Optical communication,MIMO,Field-programmable gate array,Filter (signal processing),Real-time computing,Electronic engineering,Optical performance monitoring,Phase-shift keying,Feed forward
Conference
2076-1465
Citations 
PageRank 
References 
1
0.36
5
Authors
7