Name
Abstract | ||
|---|---|---|
This paper describes the theory and implementation of a novel system for hardware synthesis from requirement spec- ifications expressed in a graphical specification language called Symbolic Timing Diagrams (STD). The system can be used together with an existing formal-verification envi- ronment for VHDL leading to a novel methodology based on the combination of synthesis and formal verification. We show the feasibility of the approach and experimental re- sults obtained with the system on the well known example of an industrial production cell, where both FPGA and ASIC hardware implementations were successfully synthesized. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/EURDAC.1996.558249 | EURO-DAC |
Keywords | Field | DocType |
hardware synthesis,requirement specification | Computer architecture,Hardware compatibility list,Computer science,Intelligent verification,High-level synthesis,Formal specification,Real-time computing,Formal methods,VHDL,High-level verification,Formal verification | Conference |
ISBN | Citations | PageRank |
0-8186-7573-X | 4 | 0.51 |
References | Authors | |
7 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Konrad Feyerabend | 1 | 4 | 0.51 |
| R. Schlör | 2 | 11 | 1.20 |