Name
Abstract | ||
|---|---|---|
Temporal blocking is a class of algorithms which reduces the required memory bandwidth (B/F ratio) of a given stencil computation, by "blocking" multiple time steps. In this paper, we prove that a lower limit exists for the reduction of the B/F attainable by temporal blocking, under certain conditions. We introduce the PiTCH tiling, an example of temporal blocking method that achieves the optimal B/F ratio. We estimate the performance of PiTCH tiling for various stencil applications on several modern CPUs. We show that PiTCH tiling achieves 1.5 similar to 2 times better B/F reduction in three-dimensional applications, compared to other temporal blocking schemes. We also show that PiTCH tiling can remove the bandwidth bottleneck from most of the stencil applications considered. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1016/j.procs.2015.05.315 | INTERNATIONAL CONFERENCE ON COMPUTATIONAL SCIENCE, ICCS 2015 COMPUTATIONAL SCIENCE AT THE GATES OF NATURE |
Keywords | Field | DocType |
Parallel computation, Stencil computation, Optimization | Bottleneck,Mathematical optimization,Memory bandwidth,Computer science,Parallel computing,Stencil,Stencil code,Algorithm,Bandwidth (signal processing) | Conference |
Volume | ISSN | Citations |
51 | 1877-0509 | 4 |
PageRank | References | Authors |
0.46 | 8 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takayuki Muranushi | 1 | 21 | 5.10 |
| Junichiro Makino | 2 | 147 | 34.17 |