Name
Abstract | ||
|---|---|---|
This paper presents the ABeeMap, a new approach to FPGA technology mapping. The mapper is based on a hybrid approach that uses pareto-dominance based asynchronous multi-objective Artificial Bee Colony associated with specific heuristics of the problem in order to find better trade-off results among area, performance and power consumption. In a set of 20 designs, we find that in comparison to state-of-the-art technology mapping, our approach is able to reduce the LUT counts and the edge counts. Placing and routing the resulting netlist leads to reduction in the configurable logic blocks count, increasing in estimated operation frequency and reduction in energy consumption. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/PATMOS.2015.7347582 | 2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) |
Keywords | Field | DocType |
FPGA,Mapping Algorithm,Artifitial Bee Colony | Netlist,Asynchronous communication,Lookup table,Computer science,Field-programmable gate array,Real-time computing,Heuristics,Mapping algorithm,Energy consumption,Power consumption | Conference |
ISSN | Citations | PageRank |
2474-5456 | 0 | 0.34 |
References | Authors | |
16 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Viviane Lucy Santos de Souza | 1 | 0 | 0.34 |
| Abel Guilhermino Silva-Filho | 2 | 62 | 12.94 |
| V. C. Wanderely | 3 | 0 | 0.34 |