Abstract | ||
---|---|---|
A non-resistance readout scheme for high density multi-level PCRAM is described. Non-resistance read metric with drift resilient nature is enhanced to be suitable for high density memory array with large parasitic time constant. 1G PCM cells in 25nm technology are structured in the form of a single bank of a 16G cell chip with the hierarchical bit-line scheme. Furthermore, 32 instances of 6bit SAR-ADC per bank are built-in with specific logic for adaptive data detection as a sense-amplifier. Experimental results for a bank of 2Gb multi-level density are demonstrated with total read latency of 450ns including word-line settling and the adaptive data detection scheme. |
Year | DOI | Venue |
---|---|---|
2015 | 10.1109/CICC.2015.7338358 | 2015 IEEE Custom Integrated Circuits Conference (CICC) |
Keywords | Field | DocType |
high density multi-level PCRAM,temporal drift mitigation,temperature compensation | Data detection,Computer science,Latency (engineering),High density,Electronic engineering,Chip,Memory array,Time constant | Conference |
Citations | PageRank | References |
2 | 0.45 | 2 |
Authors | ||
12 |
Name | Order | Citations | PageRank |
---|---|---|---|
junho cheon | 1 | 7 | 1.27 |
Insoo Lee | 2 | 10 | 1.10 |
Changyong Ahn | 3 | 9 | 1.66 |
Milos Stanisavljevic | 4 | 35 | 7.36 |
aravinthan athmanathan | 5 | 24 | 2.48 |
Nikolaos Papandreou | 6 | 2 | 0.45 |
haris pozidis | 7 | 6 | 0.90 |
Evangelos Eleftheriou | 8 | 1590 | 118.20 |
Min-Chul Shin | 9 | 9 | 2.04 |
Taekseung Kim | 10 | 9 | 2.00 |
Jong-Ho Kang | 11 | 8 | 1.37 |
Jun Hyun Chun | 12 | 39 | 5.17 |