Paper Info
Title
Low temperature multi-layer wafer level package for chip scale atomic clock (CSAC)
Abstract
This paper demonstrates a five layers wafer level packaging. This technology has been specially developed for chip scale atomic clock system package. It includes a sealed vapor cell and two supports for vertical-cavity surface-emitting lasers and photodetector. The sealed cavity is achieved by Glass-Silicon-Glass (G-S-G) anodic bonding with high hermeticity, high reliability and low bonding temperature (400°C). The triple structure is supported by two silicon wafers. It is realized by photosensitive BCB adhesive bonding with good uniformity, relatively high mechanical strength (8Mpa) and low bonding temperature (250°C). The results show that over 60% of wafer is bonded with no void on the joint area and well aligned. At last, the stacked wafer is diced into individual chips.
Year
DOI
Venue
2015
10.1109/NEMS.2015.7147472
NEMS
Keywords
Field
DocType
multi-layer bonding, wafer level package, anodic bonding, BCB adhesive bonding, CSAC
Wafer,Composite material,Thermocompression bonding,Multi layer,Wire bonding,Anodic bonding,Chip-scale atomic clock,Materials science
Conference
ISSN
Citations 
PageRank 
2474-3747
0
0.34
References 
Authors
0
6
Name
Order
Citations
PageRank
Nannan Li100.34
Yangxi Zhang201.35
ningli zhu301.01
yunhui401.35
Chengchen Gao5113.74
jing622.42