Name
Abstract | ||
|---|---|---|
A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/ISCAS.2015.7169176 | International Symposium on Circuits and Systems |
Field | DocType | ISSN |
Capacitor,Capacitance,Computer science,Electronic engineering,CMOS,Successive approximation ADC,Electrical engineering | Conference | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dante Gabriel Muratore | 1 | 0 | 1.01 |
| Edoardo Bonizzoni | 2 | 162 | 47.30 |
| Franco Maloberti | 3 | 686 | 144.70 |