Paper Info
Title
Design of a low power time to digital converter for flow metering applications
Abstract
This paper presents the design of an hybrid course-fine time to digital converter for low power applications. The core of the circuit consists of two current-mode SAR analog to digital converters working in a time-interleaved fashion. The TDC has been fully simulated at the transistor level with a 0.13-μm CMOS technology. The paper discusses the design details and the digital calibration techniques required to achieve a single-shot resolution of about 27 ps while keeping the power consumption below 600 μW.
Year
DOI
Venue
2015
10.1109/ISCAS.2015.7168966
International Symposium on Circuits and Systems
Field
DocType
ISSN
Synchronization,Capacitor,Computer science,Electronic engineering,CMOS,Mixed-signal integrated circuit,Transistor,Time-to-digital converter,Electrical engineering,Integrated injection logic,Metering mode
Conference
0271-4302
Citations 
PageRank 
References 
0
0.34
8
Authors
4
Name
Order
Citations
PageRank
Alberto Demarziani100.34
Edoardo Bonizzoni216247.30
Franco Maloberti3686144.70
Alessandro D'Amato400.34