Title
Accelerating Homomorphic Evaluation On Reconfigurable Hardware
Abstract
Homomorphic encryption allows computation on encrypted data and makes it possible to securely outsource computational tasks to untrusted environments. However, all proposed schemes are quite inefficient and homomorphic evaluation of ciphertexts usually takes several seconds on high-end CPUs, even for evaluating simple functions. In this work we investigate the potential of FPGAs for speeding up those evaluation operations. We propose an architecture to accelerate schemes based on the ring learning with errors (RLWE) problem and specifically implemented the somewhat homomorphic encryption scheme YASHE, which was proposed by Bos, Lauter, Loftus, and Naehrig in 2013. Due to the large size of ciphertexts and evaluation keys, on-chip storage of all data is not possible and external memory is required. For efficient utilization of the external memory we propose an efficient double-buffered memory access scheme and a polynomial multiplier based on the number theoretic transform (NTT). For the parameter set (n = 16384, [log(2)q] = 512) capable of evaluating 9 levels of multiplications, we can perform a homomorphic addition in 0.94 ms and a homomorphic multiplication in 48.67 ms.
Year
DOI
Venue
2015
10.1007/978-3-662-48324-4_8
CRYPTOGRAPHIC HARDWARE AND EMBEDDED SYSTEMS - CHES 2015
Keywords
Field
DocType
Homomorphic encryption, Ring learning with errors, FPGA, Reconfigurable computing
Homomorphic encryption,Polynomial,Computer science,Parallel computing,Encryption,Multiplier (economics),Multiplication,Learning with errors,Auxiliary memory,Reconfigurable computing
Conference
Volume
ISSN
Citations 
9293
0302-9743
14
PageRank 
References 
Authors
0.62
9
4
Name
Order
Citations
PageRank
Thomas Pöppelmann135717.96
Michael Naehrig2139055.23
Andrew Putnam3654.81
Adrián Macías4140.62