Name
Abstract | ||
|---|---|---|
In this paper, we characterize and solve the problem of augmenting a component-based system with time-triggered runtime verification (TTRV), where different components are expected to run on different computing cores with minimum monitoring overhead at run time. We present an optimization technique that calculates (1) the mapping of components to computing cores, and (2) the monitoring frequency, such that TTRV's runtime overhead is minimized. Although dealing with runtime overhead of concurrent systems is a challenging problem due to their inherent complex nature, our experiments show that our optimization technique is robust and reduces the monitoring overhead by 34%, as compared to various near-optimal monitoring patterns of the components at run time. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1007/978-3-319-23820-3_10 | RUNTIME VERIFICATION, RV 2015 |
Field | DocType | Volume |
Computer science,Intelligent verification,Linear temporal logic,Runtime verification,Symbolic execution,High-level verification,Multi-core processor,Software verification,Embedded system | Conference | 9333 |
ISSN | Citations | PageRank |
0302-9743 | 4 | 0.48 |
References | Authors | |
16 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Samaneh Navabpour | 1 | 79 | 5.78 |
| Borzoo Bonakdarpour | 2 | 490 | 45.02 |
| Sebastian Fischmeister | 3 | 409 | 52.75 |