Name
Abstract | ||
|---|---|---|
This paper describes a 3D computer architecture designed to achieve the lowest possible power consumption for “embedded applications” like radar and signal processing. It introduces several unique concepts including a low-power SIMD tile, low-power 3D memories, and 3D and 2.5D interconnect that is circuit switched so it can be tuned at run-time for a specific application. When conservatively projected to the 7 nm node, simulations of the architecture show potential for exceeding 75 GFLOPS/W, about 20x better than today's CPUs and GPUs. This translates to 13 pJ/FLOP. This paper will focus on the 3D specific aspects of the design. This architecture is highly suited to DSP and multimedia workflows. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/3DIC.2014.7152143 | 2014 International 3D Systems Integration Conference (3DIC) |
Keywords | Field | DocType |
SIMD,radar processing,low-power CPU,low-power GPU,low-power MPI,3DIC,2.5D | Signal processing,Computer architecture,Digital signal processing,Architecture,Circuit switching,FLOPS,Computer science,SIMD,Interconnection,Benchmark (computing),Embedded system | Conference |
ISSN | Citations | PageRank |
2164-0157 | 0 | 0.34 |
References | Authors | |
2 | 12 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Paul D. Franzon | 1 | 634 | 83.24 |
| Eric Rotenberg | 2 | 1151 | 108.62 |
| James Tuck | 3 | 25 | 3.79 |
| Huiyang Zhou | 4 | 994 | 63.26 |
| W. Rhett Davis | 5 | 563 | 59.37 |
| Hongwen Dai | 6 | 28 | 3.14 |
| Joonmoo Huh | 7 | 2 | 1.04 |
| Sunkgwan Ku | 8 | 0 | 0.34 |
| Steve Lipa | 9 | 27 | 3.96 |
| Chao Li | 10 | 132 | 6.04 |
| Jong Beom Park | 11 | 0 | 0.68 |
| Joshua Schabel | 12 | 0 | 2.37 |