Name
Title | ||
|---|---|---|
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit |
Abstract | ||
|---|---|---|
In this paper, an electrical interconnect test method and a built-in test circuit are proposed to detect and locate open defects in a 3D stacked IC made of dies, in which ESD protection circuits are not embedded. The test method is based on quiescent supply current that is made flow through the interconnect to be tested only in the tests. Feasibility of the tests is evaluated by Spice simulation. The simulation results show that open defects in a 3D stacked IC not embedding ESD protection circuits are detected by the test method, like in the tests of ICs embedding ESD protection circuits. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/3DIC.2015.7334592 | 3DIC |
Keywords | Field | DocType |
interconnect test, supply current test, design for testabiligy, built-in test circuit, TSV, open defect | Test method,Embedding,Interconnect test,Spice,Electronic engineering,Integrated circuit design,Die (manufacturing),Engineering,Electronic circuit,Interconnection,Electrical engineering | Conference |
ISSN | Citations | PageRank |
2164-0157 | 0 | 0.34 |
References | Authors | |
8 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kosuke Nanbara | 1 | 0 | 0.34 |
| Akihiro Odoriba | 2 | 0 | 0.34 |
| Masaki Hashizume | 3 | 98 | 27.83 |
| Hiroyuki Yotsuyanagi | 4 | 2 | 1.41 |
| Shyue-Kung Lu | 5 | 259 | 34.09 |