Paper Info
Title
From signal temporal logic to FPGA monitors
Abstract
Due to the heterogeneity and complexity of systems-of-systems (SoS), their simulation is becoming very time consuming, expensive and hence impractical. As a result, design simulation is increasingly being complemented with more efficient design emulation. Runtime monitoring of emulated designs would provide a precious support in the verification activities of such complex systems. We propose novel algorithms for translating signal temporal logic (STL) assertions to hardware runtime monitors implemented in field programmable gate array (FPGA). In order to accommodate to this hardware specific setting, we restrict ourselves to past and bounded future temporal operators interpreted over discrete time. We evaluate our approach on two examples: the mixed signal bounded stabilization property and the serial peripheral interface (SPI) communication protocol. These case studies demonstrate the suitability of our approach for runtime monitoring of both digital and mixed signal systems.
Year
DOI
Venue
2015
10.1109/MEMCOD.2015.7340489
MEMOCODE
Keywords
Field
DocType
signal temporal logic,FPGA monitors,SoS heterogeneity,SoS complexity,systems-of-systems,design simulation,design emulation,verification activities,complex systems,STL assertions,hardware runtime monitoring,field programmable gate array,hardware specific setting,temporal operators,discrete time,mixed signal bounded stabilization property,serial peripheral interface,SPI communication protocol,digital signal systems,mixed signal systems
Logic gate,Computer science,Simple programmable logic device,Programmable logic array,Field-programmable gate array,Real-time computing,Runtime verification,Emulation,Communications protocol,Hardware emulation,Embedded system
Conference
Citations 
PageRank 
References 
22
0.77
18
Authors
6
Name
Order
Citations
PageRank
Stefan Jaksic1554.21
Ezio Bartocci273357.55
Radu Grosu3101197.48
Reinhard Kloibhofer4220.77
Thang V. Nguyen535148.76
Dejan Nickovic674340.88