Paper Info
Title
11.7 A load-aware pre-emphasis column driver with 27% settling-time reduction in ±18% panel-load RC delay variation for 240Hz UHD flat-panel displays.
Abstract
As the panel size and resolution of flat-panel displays grow, the one-horizontal (1-H) time, in which a column driver should program data voltage into a row of pixels, is reduced and becomes a main bottleneck to realize high-resolution displays [1]. An ultra-high-definition display (UHD, 3840 RGB × 2160) requires column drivers to program the data voltage within the 1.8µs 1-H time required for a frame rate of 240Hz. However, the settling time from the driver to the pixel is strictly limited by display panel load resistance (RL) and capacitance (CL). Also, the RLCL delay becomes larger as panel size grows. Although a dual-driving method, in which the column drivers are assembled at both ends of columns, can double the 1-H time and reduce the RLCL delay by a factor of 4, it increases the bezel width and cost of a display device. To overcome the RLCL delay and reduce the settling time, pre-emphasis driving methods have been proposed [2–4]. However, the common problem of previous works is that the settling time can vary widely under column-to-column RLCL variation as depicted in the waveform in Fig. 11.7.1. The graph in Fig. 11.7.1 plots the settling time of the data voltage (vD) to the end of the data line (vP) within 0.7% of ΔV for four different values of K from a behavioral simulation. The settling time can be even longer with a smaller RLCL. This is because the pre-emphasis factor K (the ratio of an overdriven voltage step (K·ΔV) to a data voltage step (ΔV)) and the pre-emphasis duration (TPRE) are globally fixed. This CLeaRLy shows that the settling time with a fixed K and the K value for the point of the shortest settling time significantly changes according to the column-to-column RLCL variation, which cannot be measured for each column because of the large number of columns (3840×3) in the UHD display panel. Moreover, the K value, determined by passive components such as the method in [2], can suffer from process variation among channels. This also results in settling time variation.
Year
Venue
Field
2016
ISSCC
Capacitance,Computer science,Settling time,Waveform,Voltage,Electronic engineering,Display device,RC time constant,Process variation,Emphasis (telecommunications)
DocType
Citations 
PageRank 
Conference
0
0.34
References 
Authors
1
9
Name
Order
Citations
PageRank
Jun-suk Bang1114.24
Hyunsik Kim231.93
Kye-Seok Yoon352.12
Sang-Han Lee421.06
Se-Hong Park500.68
Ohjo Kwon641.65
Choongsun Shin721.22
Seonki Kim800.34
Gyu-Hyeong Cho940176.39