Name
Abstract | ||
|---|---|---|
To support growing data bandwidths, high-speed moderate-resolution ADCs have become vital for high-speed serial links. Interleaved SAR ADCs achieve high sampling speeds and good energy efficiency. However a challenge is that these ADCs are large and therefore suffer from interleaving artifacts related to size [1]. Compact, efficient SAR ADCs are needed to address this problem. As an alternative, multiple-bit-per-cycle SAR ADCs deliver high speed from a single SAR ADC, but at the cost of significant added complexity (i.e., extra quantizers and capacitor DACs) and die area [2,3]. This work addresses the need for a fast, compact SAR ADC, with a 1GS/s SAR ADC that has the best Walden FOM and the smallest area among 5-to-6.3b ADCs published in ISSCC (see Fig. 27.3.1). |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISSCC.2016.7418106 | International Solid-State Circuits Conference |
Field | DocType | ISBN |
Flight dynamics (spacecraft),Capacitor,Computer science,Efficient energy use,Linearity,Electronic engineering,Charge injection,Successive approximation ADC,Electrical engineering,Distortion,Interleaving | Conference | 978-1-4673-9466-6 |
Citations | PageRank | References |
16 | 1.32 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyo-jin Choo | 1 | 41 | 8.52 |
| Bell, J.T. | 2 | 19 | 2.90 |
| Michael P. Flynn | 3 | 74 | 8.98 |