Name
Title | ||
|---|---|---|
2.9 A 2GHz 244fs-resolution 1.2ps-Peak-INL edge-interpolator-based digital-to-time converter in 28nm CMOS |
Abstract | ||
|---|---|---|
Digital-to-time converters (DTC) generate a clock with a time delay (or phase shift) based on a digital input code. They can be used in clock-and-data-recovery (CDR) circuits [1,2], in the feedback or reference path of a phase-locked loop (PLL) [3,4] or as direct phase modulators in outphasing transmitters (OT) [5]. While DTCs in PLLs often operate close to the reference oscillator frequency, CDR and OT DTCs are required to operate at frequencies in the GHz range. DTCs are often built using a multistage segmented architecture, employing separate coarse and fine delay tuning. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISSCC.2016.7417902 | 2016 IEEE International Solid-State Circuits Conference (ISSCC) |
Keywords | Field | DocType |
edge-interpolator-based digital-to-time converter,CMOS,digital-to-time converters,time delay,phase shift,digital input code,clock-and-data-recovery circuits,CDR circuits,phase-locked loop,PLL,direct phase modulators,outphasing transmitters,multistage segmented architecture,current 2.9 A,frequency 2 GHz,time 244 fs,time 1.2 ps,size 28 nm | Clock signal,Phase-locked loop,Oscillation,Computer science,Interpolation,Electronic engineering,Converters,CMOS,Electronic circuit,Electrical engineering,Phase (waves) | Conference |
ISBN | Citations | PageRank |
978-1-4673-9466-6 | 3 | 0.43 |
References | Authors | |
4 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sebastian Sievert | 1 | 9 | 0.94 |
| Ofir B. Degani | 2 | 107 | 12.13 |
| Assaf Ben Bassat | 3 | 3 | 0.43 |
| Rotem Banin | 4 | 11 | 2.43 |
| Ashoke Ravi | 5 | 176 | 26.87 |
| Bernd-Ulrich Klepser | 6 | 9 | 0.94 |
| Zdravko Boos | 7 | 9 | 1.62 |
| Doris Schmitt-landsiedel | 8 | 260 | 50.73 |