Name
Title | ||
|---|---|---|
6.7 A 1.2e− temporal noise 3D-stacked CMOS image sensor with comparator-based multiple-sampling PGA |
Abstract | ||
|---|---|---|
This paper presents a 1.2e-, 3D-stacked CMOS image sensor (CIS) for mobile applications. A key motivation for using a stacked configuration is to minimize the chip area. Also, since numerous components must be integrated into the bottom chip, a scaled 65nm CMOS process is adopted for the bottom chip. The developed CIS features 1.2e- temporal noise with extremely high power efficiency by employing a multiple-sampling (MS) technique. A 2nd-order incremental ΔΣ ADC with inverter-based switched-capacitor integrator realizes the MS technique with low power [1]. However, an exponential number of samples are required to reduce the quantization noise, and conversion speed worsens with higher bit resolution. An extended counting ADC, which is a blend of folding integration and cyclic ADC, attains high resolution with reduced conversion time [2-3]. However, an op-amp with high open-loop gain is required for good linearity and column-to-column matching characteristics, which increases power consumption. Also it is not suitable for scaled CMOS technology. An alternative approach is a single-slope (SS) based MS technique [4], in which two SS-ADCs convert the same pixel signal, and the readout signal is averaged in the digital domain, but the noise improvement is limited to -3dB and the power consumption and area occupation are roughly doubled. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISSCC.2016.7417937 | 2016 IEEE International Solid-State Circuits Conference (ISSCC) |
Keywords | Field | DocType |
noise improvement,readout signal,pixel signal,SS-ADC,single-slope based MS technique,power consumption,linearity characteristics,column-to-column matching characteristics,open-loop gain,op-amp,conversion time reduction,folding integration,cyclic ADC,conversion speed reduction,quantization noise reduction,inverter-based switched-capacitor integrator,2nd-order incremental ΔΣ ADC,power efficiency,scaled CMOS process,chip area minimization,mobile applications,CIS,comparator-based multiple-sampling PGA,1.2e- temporal noise 3D-stacked CMOS image sensor,size 65 nm | Inverter,Comparator,Noise measurement,Image sensor,Computer science,Integrator,Chip,Electronic engineering,CMOS,Quantization (signal processing),Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-4673-9466-6 | 2 | 0.37 |
References | Authors | |
3 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| kei shiraishi | 1 | 9 | 1.82 |
| Yasuhiro Shinozuka | 2 | 2 | 1.05 |
| Tomonori Yamashita | 3 | 2 | 0.37 |
| Kazuhide Sugiura | 4 | 7 | 1.02 |
| Naoto Watanabe | 5 | 2 | 0.37 |
| Ryuta Okamoto | 6 | 10 | 2.00 |
| tatsuji ashitani | 7 | 3 | 0.75 |
| Masanori Furuta | 8 | 17 | 4.42 |
| Tetsuro Itakura | 9 | 187 | 33.44 |