Name
Abstract | ||
|---|---|---|
Modular test and hierarchical test of core-based System-on-Chip (SoC) are two widely used SoC test methodologies. In this paper, the hybrid test methodology that incorporates these two together is studied by using an industrial real case. Thorough experimental results are demonstrated to compare various scenarios of the hybrid hierarchical and modular tests for SoC designs. Based on the experimental results, using channel sharing based modular test technology at a group of cores combined with hierarchical test to map the patterns of core groups to the top level would result in the most efficient total test time. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/NATW.2015.9 | NATW |
Keywords | Field | DocType |
SoC Testing,Modular Testing,Hierarchical Testing,EDT | Broadcasting,Test method,Automatic test pattern generation,Computer architecture,System on a chip,Communication channel,Modular design,Engineering,Hierarchical test,Embedded system | Conference |
Citations | PageRank | References |
3 | 0.51 | 7 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guoliang Li | 1 | 16 | 4.97 |
| Jun Qian | 2 | 63 | 10.39 |
| Qinfu Yang | 3 | 11 | 2.49 |
| Yuan Zuo | 4 | 16 | 2.08 |
| Rui Li | 5 | 9 | 1.74 |
| Yu Huang | 6 | 186 | 11.96 |
| Mark Kassab | 7 | 654 | 48.74 |
| Janusz Rajski | 8 | 2460 | 201.28 |