Name
Abstract | ||
|---|---|---|
New many-core architectures such as Intel Xeon Phi offer applications significantly higher power efficiency than conventional multi-core processors. However, while this processor's compute and communication performance is an excellent match for MPI applications, leveraging its potential in practice has proven difficult because of the mismatch between the MPI distributed memory model and this processor's shared memory communication hardware. Hybrid MPI is a high performance portable implementation of MPI designed for communication over shared memory hardware. It shares the heaps of all the MPI processes that run on the same node, enabling them to communicate directly without unnecessary copies. This paper describes our work to port Hybrid MPI to the Xeon Phi platform, demonstrating that Hybrid MPI offers better performance than the native Intel MPI implementation in terms of memory bandwidth, latency and benchmark performance. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1145/2612262.2612267 | ROSS@ICS |
Field | DocType | Citations |
Memory bandwidth,Shared memory,Xeon Phi,Computer science,Latency (engineering),Parallel computing,Hybrid kernel,Distributed memory,Heap (data structure),Operating system | Conference | 1 |
PageRank | References | Authors |
0.37 | 4 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| U. S. Wickramasinghe | 1 | 4 | 1.77 |
| Greg Bronevetsky | 2 | 949 | 44.91 |
| Andrew Lumsdaine | 3 | 2754 | 236.74 |
| Andrew Friedley | 4 | 39 | 2.47 |