Paper Info
Title
Si Elegans: Hardware Architecture And Communications Protocol
Abstract
The hardware layer of the Si elegans EU FP7 project is a massively parallel architecture designed to accurately emulate the C. elegans nematode in biological real-time. The C. elegans nematode is one of the simplest and well characterized Biological Nervous Systems (BNS) yet many questions related to basic functions such as movement and learning remain unanswered. The hardware layer includes a Hardware Neural Network (HNN) composed of 302 FPGAs (one per neuron), a Hardware Muscle Network (HMN) composed of 27 FPGAs (one per 5 muscles) and one Interface Manager FPGA, which is physically connected through 2 Local Area Networks (LANs) and through an innovative 3D optical connectome. Neuron structures (gap junctions and synapses) and muscles are modelled in the design environment of the software layer and their simulation data (spikes, variable values and parameters) generate data packets sent across the Local Area Networks (LAN). Furthermore, a software layer gives the user a set of design tools giving the required flexibility and high level hardware abstraction to design custom neuronal models. In this paper the authors present an overview of the hardware layer, connections infrastructure and communication protocol.
Year
Venue
Keywords
2015
2015 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN)
Field Programmable Gate Array (FPGA), C. elegans, Hardware Neural Network(HNN), Biological Nervous System (BNS)
Field
DocType
ISSN
Computer science,Network packet,Field-programmable gate array,Hardware abstraction,Software,Local area network,Artificial neural network,Embedded system,Hardware architecture,Communications protocol
Conference
2161-4393
Citations 
PageRank 
References 
2
0.46
5
Authors
5
Name
Order
Citations
PageRank
Pedro Machado1114.61
Kofi Appiah216318.09
T. Martin Mcginnity351866.30
T. Martin Mcginnity451866.30
John J. Wade51028.91