Early detection and repair of VRT and aging DRAM bits by margined in-field BIST

Paper Info

Title
Early detection and repair of VRT and aging DRAM bits by margined in-field BIST

Abstract
We propose improving system availability by performing in-field repair at the chip level. This enables margining and detection of degrading memory cells before the user observes any errors. A 576 Mb embedded DRAM at 1.5 GHz in a 40nm CMOS technology achieves improved resilience to both aging memory cells and cells with variable retention time (VRT). Un-interrupted user access of 6 billion 72-bit read and write operations per second is maintained during background repair.

Year	DOI	Venue
2014	10.1109/VLSIC.2014.6858414	VLSIC
Field	DocType	Citations
Dram,Early detection,Computer science,Parallel computing,Electronic engineering,CMOS,Chip,Embedded system	Conference	2
PageRank	References	Authors
0.39	4	24

Authors (24 rows)

Cited by (2 rows)

References (4 rows)

Name	Order	Citations	PageRank
Bendik Kleveland	1	26	3.91
Jeong Choi	2	3	1.49
Jeff Kumala	3	2	0.39
Pascal Adam	4	5	1.17
Patrick Chen	5	2	0.39
Rajesh Chopra	6	3	1.15
Antonio Cruz	7	2	0.39
Ronald B. David	8	7	1.94
Ashish Dixit	9	33	2.42
Sinan Doluca	10	2	0.39
Mark Hendrickson	11	2	0.39
Ben Lee	12	3	0.81
Ming Liu	13	3	1.15
Michael John Miller	14	2	0.73
Mike Morrison	15	2	0.73
Byeong Cheol Na	16	3	0.81
Jay Patel	17	18	8.57
Dipak K. Sikdar	18	3	1.15
Michael Sporer	19	2	0.39
Clement Szeto	20	3	0.81
Anju Tsao	21	2	0.39
Jianguang Wang	22	2	0.39
Daniel Yau	23	2	0.39
Wesley Yu	24	2	0.39