Name
Title | ||
|---|---|---|
7.4μW Ultra-high slew-rate pseudo single-stage amplifier driving 0.1-to-15nF capacitive load with >69° phase margin |
Abstract | ||
|---|---|---|
To achieve ultra-high slew-rate with stable operation under wide capacitive load range, pseudo single-stage amplifier is proposed in this paper. The proposed amplifier achieves widest capacitive load drivability (x150). Also, this work achieves at least 151 times larger FOM for slew-rate compared to state-of-the-art works. This chip was fabricated using a 0.18 μm CMOS process with area of 0.0021 mm2. |
Year | DOI | Venue |
|---|---|---|
2015 | 10.1109/VLSIC.2015.7231297 | VLSIC |
Field | DocType | ISBN |
Logic gate,Capacitor,Computer science,Power factor,Feedback loop,Electronic engineering,Chip,Phase margin,Slew rate,Amplifier | Conference | 978-4-86348-502-0 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sung-Wan Hong | 1 | 50 | 12.32 |
| Gyu-Hyeong Cho | 2 | 401 | 76.39 |