Paper Info
Title
A power controlled RF CMOS class-E PA with 43% maximum efficiency in 2.2 GHz
Abstract
This paper proposes a 2.2 GHz CMOS Power Amplifier (PA) useful to S-Band applications with an effective 3-bit output power control for efficiency improvement. It is composed by a cascode amplifier topology to minimize the voltage stress across the power transistors, being the cascode amplifier composed by four parallel branches, where the state (on or off) of 3 branches is separately activated by a 3-bit input, for efficiency control. It was designed for the 1 W output power range in 130 nm CMOS process. Post-layout simulations resulted a peak output power of 28.1 dBm (near 650 mW) with a maximum output power efficiency around 43% under 3.3 V of supply voltage. The 3-bit control allows a total output power dynamic range adjustment of 5.7 dBm, divided in 7 steps, with the efficiency changing from 25.4% to 43.7%.
Year
DOI
Venue
2015
10.1109/ICECS.2015.7440258
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
Keywords
Field
DocType
CMOS power amplifier,power controlled RF CMOS class-E PA,S-Band applications,cascode amplifier topology,voltage stress,power transistors,CMOS process,post-layout simulations,power efficiency,3-bit control,power dynamic range adjustment,frequency 2.2 GHz,power 1 W,size 130 nm,voltage 3.3 V
Electrical efficiency,Computer science,Power factor,Electronic engineering,Control engineering,Linear amplifier,Power supply rejection ratio,Power-added efficiency,RF power amplifier,Electrical engineering,Power bandwidth,Switched-mode power supply
Conference
Citations 
PageRank 
References 
0
0.34
5
Authors
4
Name
Order
Citations
PageRank
Diogo B. Santana100.34
hamilton klimach27120.07
Eric E. Fabris31911.33
sergio bampi4496102.12